1. Field of the Invention
The present invention generally relates to a field effect thin-film transistor and a method of manufacturing the same as well as a semiconductor device provided with the above transistors. In particular, to a field effect thin-film transistor (TFT) applicable to a static semiconductor memory device which includes memory cells formed of insulated gate field effect transistors (MOSFETs) and a method of manufacturing the same.
2. Description of the Background Art
A so-called static random access memory (SRAM) has been well known as one type of static semiconductor memory device. Since the present invention can achieve the most preferable effect when applied to the SRAM, description will be made on the SRAM.
In connection with the SRAM, effort has been made for increasing degree of integration and reducing a standby current. Memory cells of a high resistance load type have been used for increasing the degree of integration. In order to reduce power consumption of SRAM including the high resistance load memory cells, however, it is necessary to increase the resistance value of the high resistance load used in the memory cell. Also in the SRAM, increase of the degree of integration of the memory cells correspondingly requires increase of the resistance value of the high resistance load. Meanwhile, Increase of resistance value of the high resistance load deteriorates stability of operation of the memory cells. In connection with the SRAM having a degree of integration of 4M bit or more, therefore, change from the high resistance load type to a CMOS type has been studied in order to avoid instability in operation of the memory cells.
The CMOS memory cell is formed of four n-channel MOS transistors and two p-channel transistors. If these six transistors were formed on a substrate of silicon monocrystal, an area occupied by the memory cell would be one and half times as large as that of the memory cell of the high resistance load type, so that reduction of the area occupied by the memory cell would become difficult. In order to increase the degree of integration to a higher extent, a so-called TFT load complete type CMOS memory cell of a three-dimensional structure has been developed, in which two p-channel MOS transistors are formed of thin-film transistors using polysilicon and disposed above four n-channel MOS transistors formed of a monocrystal silicon substrate.
FIG. 83 is an equivalent circuit diagram showing one memory cell M in an SRAM of the complete or fully CMOS type in the prior art. As shown in FIG. 83, inverter circuits, which are formed of two n-channel driver MOS transistors Q2 and Q4 as well as two p-channel load MOS transistors Q1 and Q3, respectively, are cross-coupled to form a flip-flop circuit. The flip-flop circuit includes two storage nodes (N1 and N2) connected to n-channel access transistors Q5 and Q6, respectively. A power supply voltage Vcc and a ground potential Vss are supplied to the flip-flop circuit. Drains of the access transistors Q5 and Q6 are connected to bit lines 33 and 34. Gate electrodes of the access transistors Q5 and Q6 are connected to a word line 35. As is well known, the SRAM thus constructed operates as follows. In a standby state, the word line 35 as well as bit lines 33 and 34 are held at 0 V, the access transistors Q5 and Q6 are in an OFF-state, and thus the flip-flop circuit is isolated. Thereby, the storage node N1 (or N2) holds "High" (3 V) as data, and the storage node N2 (or N1) holds "LOW" (0 V) as data. Hold of data is carried out by holding electric charges accumulated in floating capacities in the storage nodes N1 and N2.
When a desired memory cell is selected, i.e., when the word line 35 is at the "High" level, the access transistors Q5 and Q6 are turned on. Thereby, the storage nodes N1 and N2 become conductive to the bit lines 33 and 34. In this operation, voltages corresponding the states of the storage nodes N1 and N2 appear on the bit lines 33 and 34 through the access transistors Q5 and Q6, respectively. In this manner, information held in the memory cell is read. For writing data into the memory cell, the access transistors Q5 and Q6 are maintained in the ON-state, and voltages corresponding to the desired states to be written are applied to the bit lines 33 and 34, respectively. In the reading/writing operations, as described above, the word line 35 is raised, and information of "High" or "Low" is stored from the bit lines 33 and 34 through the access transistors Q5 and Q6 into the storage nodes N1 and N2, or conversely, information is read from the storage nodes N1 and N2, whereby the memory cell functions as a static memory device. In the standby state of the memory cell of the SRAM having the CMOS circuit described above, only a leak current of the MOS transistor flows. Therefore, the SRAM of the complete CMOS type has a feature that the power consumption is extremely small.
FIG. 84 is an equivalent circuit diagram showing a three-dimensional arrangement of a memory cell of a complete CMOS SRAM of a TFT load type in the prior art. FIGS. 85A and 85B as well as FIG. 86 are schematic plans and a cross section showing a memory cell of the SRAM of the TFT load type in the prior art. Referring to FIGS. 84-86, the memory cell of the SRAM of the TFT load type in the prior art will be described below.
Referring to FIG. 84, an upper active element layer (will be referred to as an upper layer) is provided with the p-channel MOS transistors Q1 and Q3, each of which is integrally connected at its one electrode to the power supply Vcc. In the upper layer, a gate electrode of the p-channel MOS transistor Q1 and the other electrode of p-channel MOS transistor Q3 are integrally connected together at a node N21. A gate electrode of the p-channel MOS transistor Q3 and the other electrode of p-channel MOS transistor Q1 are integrally connected together at a node N11. The upper layer is also provided with the bit lines 33 and 34.
A lower active element layer (will be referred to as a lower layer) is provided with the n-channel MOS transistors Q2, Q4, Q5 and Q6. One electrode of each of the n-channel MOS transistors Q2 and Q4 is integrally connected to the ground electrode Vss. In the lower layer, a gate electrode of n-channel MOS transistor Q2 and the other electrode of n-channel MOS transistor Q4 are integrally connected together at a node N22, and a gate electrode of n-channel MOS transistor Q4 and the other electrode of n-channel MOS transistor Q2 are integrally connected together at a node N12. The lower layer is further provided with the word line 35.
The upper and lower layers are isolated from each other by an insulating layer. The insulating layer is provided with a through hole 51 for electrically connecting the node N11 in the upper layer to the node N12 in the lower layer, and is also provided with a through hole 52 for electrically connecting the node N21 in the upper layer and the node N22 in the lower layer. The CMOS flip-flop circuit is formed by connecting the MOS transistors Q1, Q2, Q3 and Q4 through the holes 51 and 52 in this manner.
Further in the lower layer, one electrode of the access n-channel MOS transistor Q5 is connected to the node N12, and a gate electrode thereof is connected to the word line 35. Similarly, one electrode of the n-channel MOS transistor Q6 is connected to the node n22, and a gate electrode thereof is connected to the word line 35. The other electrode of n-channel MOS transistor Q5 is electrically connected to the bit line 33 provided in the upper layer through a through hole 53 provided in the insulating layer. Similarly, the other electrode of n-channel MOS transistor Q6 is connected to the bit line 34 in the upper layer through a through hole 54.
FIGS. 85A and 85B are plans showing planar layouts of active elements in the upper and lower layers of the memory cell in SRAM shown in FIG. 84, respectively. Referring to FIG. 85A, the upper layer is provided with an active layer 55 which is made of polysilicon and is located on gate electrodes 60 with a gate insulating film therebetween. Regions of the active layer 55 not overlapping the gate electrodes 60 contain a large amount of boron (B) introduced thereinto to form p.sup.+ regions. Thereby, the p-channel MOS transistors (TFTs) Q1 and Q3 are formed. Active elements in the upper layer have bottom gate structures in which the gate electrodes 60 are located under the active layers 55.
Referring to FIG. 85B, the lower layer is provided with active layers 56 located in a p.sup.- region of the semiconductor substrate. Gate electrodes 71 are formed on the active layers 56 with a gate insulating film therebetween. Regions of the active layers 56 not overlapping the gate electrodes 71 contain a large amount of arsenic (As) introduced thereinto to form n.sup.+ regions. Thereby, n-channel MOS transistors Q2, Q4, Q5 and Q6 are formed.
The through holes 51, 52, 53 and 54 are provided for electrically connecting the upper and lower layers to each other as described above. The nodes N11 and N12 as well as the through holes for connecting them are two in number, respectively, which is determined in view of arrangement of them. In FIGS. 85A and 85B, there are shown neither an aluminum interconnections forming the ground line (Vss line) and bit lines 33 and 34 nor aluminum interconnections for reinforcing the word lines (gate electrodes) 71 at portions spaced by every several tens of bits. In the structure shown in FIGS. 85A and 85B, two aluminum interconnections forming the bit lines 33 and 34 are provided parallel to line L--L and contain the through holes 53 and 54. Aluminum interconnections for reinforcing the word lines 71, which are disposed above and parallel to the word line 71, serve to prevent drop of potential which may be caused by the electrical resistance of the word lines 71.
FIG. 86 is a schematic cross section showing a sectional structure taken along line L--L in FIGS. 85A and 85B. Referring to FIG. 86, brief description will be made on the sectional structure of the memory cell of SRAM in the prior art and a method of manufacturing the same.
A monocrystal silicon substrate 1 forms a p.sup.- region which is located at a main surface side in the memory cell region and contains impurity at a concentration of about 10.sup.18 /cm.sup.3 The silicon substrate 1 is provided at its main surface with an isolating oxide film 21 of 4000 .ANG. in thickness formed by an LOCOS method. A gate oxide film 41 of 100 .ANG. in thickness is formed on the main surface of silicon substrate 1. Each region isolated by the isolating oxide film 21 forms an active layer 56. The gate electrode 71 is formed on the region of active layer 56 in accordance with a predetermined pattern. The gate electrode 71 is formed of a polysilicon layer of 1500 .ANG. in thickness, which contains phosphorus at a concentration of 10.sup.20 /cm.sup.3, and a tungsten silicide (WSi.sub.2) layer of 2000 .ANG. in thickness. Arsenic is implanted at a dosage of 2.times.10.sup.15 /cm.sup.2 from above the patterned gate electrodes 71 to form source/drain regions (n.sup.+ regions) 56b of the n-channel MOS transistors Q2, Q4, Q5 and Q6, i.e., regions of the active layers 56 over which the gate electrodes 71 are not located. Regions of the active layers 56 overlapping the gate electrodes 71 form channel regions 56a. An insulating film, i.e., oxide film is deposited by the CVD method on the gate electrode 71, and the interlayer insulating film 42 is formed therefrom after flattening the surface thereof. The interlayer insulating film 42 has a thickness of about 3000 .ANG..
The through holes 51 and 52 as well as through holes 53 and 54 (through holes 51 and 53 are not shown in FIG. 86) for the nodes N12 and N22 are opened in the interlayer insulating film 42. In the through holes 51, 52, 53 and 54, there are formed electrically conductive films 81 each of which is formed of a polysilicon layer of 2000 .ANG. in thickness and containing arsenic at a concentration of 2.times.10.sup.20 /cm.sup.3 and a tungsten silicide layer of 2000 .ANG. in thickness. Over the through holes 51 and 52, there is deposited a polysilicon layer of 2000 .ANG. in thickness, which contains arsenic at a concentration of 2.times.10.sup.20 /cm.sup.3 and is patterned to form the gate electrodes 60 in the upper layer. On the gate electrodes 60, there is formed the oxide film, i.e., gate insulating film 43 of 200 .ANG. in thickness by the CVD method. On the gate insulating film 43, there is deposited a polysilicon layer of 300 .ANG. in thickness by the CVD method, which is patterned to form the active layers 55 in the upper layer. This deposition of the polysilicon layer is carried out at a temperature of 620.degree. C. Portions of the gate insulating film 43 located above the through holes 51 and 52 are removed for the electrical connection to the lower layer. In the active layer 55, boron (B) is introduced into portions above the through holes 51 and 52 and portions not overlapping the gate insulating film 43 at a concentration of 2.times.10.sup.20 /cm.sup.3 for forming the source/drain regions 55b (see FIG. 85A) of the p-channel MOS transistors Q1 and Q3. Similarly to the lower layer, a flattened interlayer insulating film 44 is formed at a thickness of about 3000 .ANG.. The through holes 53 and 54 are opened again, and an aluminum interconnection layer 91 of 7000 .ANG. in thickness is deposited and patterned to form the bit line 34 (FIG. 84) and the bit line 33 which cannot be seen in FIG. 86. Further, there is formed an interlayer insulating film 45, i.e., oxide film of 7000 .ANG. in thickness by a plasma CVD method. On the interlayer insulating film 45, there is formed an aluminum interconnection layer 92 by depositing a layer of 8000 .ANG. in thickness and patterning the same, for reinforcing the word line 35 (gate electrodes 71 in FIGS. 85B and 86). In this manner, the memory cell of the complete CMOS SRAM of the TFT load type is completed in the prior art. In FIG. 86, the ground line (Vss line) is not shown.
The conventional TFT (p-channel MOS transistor) has an electric characteristic such as shown in FIG. 87, which shows a relationship between a drain current (I.sub.D) and a gate voltage (V.sub.G) when a drain voltage V.sub.D of -3 V is applied in a TFT having a channel length of 0.8 .mu.m and a channel width of 0.4 .mu.m. At the gate voltage V.sub.G of -3 V (ON state), the drain current I.sub.D is 1 nA (10.sup.-9 A), and at the gate voltage V.sub.G of 0 V (OFF state), the drain current I.sub.D is 100 fA (10.sup.-13 A).
High integration of SRAM naturally requires miniaturization of elements forming the memory cell. For example, in the SRAM of 16M bit, a design size of an element is in a range from 0.35 to 0.4 .mu.m. Miniaturization of elements to such a size causes a problem that the memory cell of SRAM does not operate due to the reasons which will be described below.
If the size of an element is miniaturized to 0.4 .mu.m or less, a power supply voltage used for the same is reduced to 3.3 V or 3 V for ensuring reliability of a transistor. Further, in connection with B (will be expressed as .beta..sub.D) of the driver transistor Q2 or Q4 and B (will be expressed as .beta..sub.A) of the access transistor Q5 or Q6 in the lower layer, a ratio of .beta..sub.D /.beta..sub.A (will be referred to as .beta. ratio) takes a value of about 2, and cannot be sufficiently large. .beta. is an amount expressing conductance of the transistor, and can be given by an expression of .beta.=.mu..epsilon..sub.OX .epsilon..sub.0 W(T.sub.OX L) where .mu. is a degree of displacement, .epsilon..sub.OX is a relative dielectric constant of the gate insulating film, .epsilon..sub.0 is a dielectric constant of the vacuum, t.sub.OX is a thickness of the gate oxide film, W is a gate width and L is a gate length.
In an equivalent circuit in FIG. 83, information stored in the memory cell is read by applying the voltage Vcc to both the bit lines 33 and 34 and applying a positive voltage to the word line 35 for rendering conductive the access transistors Q5 and Q6. Thereby, the bit line is discharged at the driver transistor Q2 or Q4 at the "Low" level side in the memory cell (the driver transistors in the "Low" level side being in the ON state), whereby the potential of the bit line connected to the "Low" level side in the memory cell becomes lower than the potential of the bit line connected to the "High" level side and thus information held in the memory cell is transmitted to the bit line. In this reading operation, it is assumed that the node N2 maintains the potential of "Low" level (0 V) and the node N1 maintains the potential of "High" level (3 V). In this case, a current flows from the bit line 34 through the transistors Q6 and Q4 to the ground potential Vss (0 V) because the transistors Q4 and Q6 are in the ON state. The potential at the crossing between the bit line 34 receiving the voltage Vcc (3 V) and the transistor Q6 decreases from 3 V to 1.5 V due to the resistance of the bit line 34 itself. If the .beta. ratio were sufficiently large, the potential of the node N2 would be maintained at a value near 0 V. In the case of the .beta. ratio of 2, however, the resistance (inverse number of conductance) of the transistor Q6 in ON state is twice as large as that of the transistor Q4, so that the potential of node N2 increases to 0.5 V due to resistance division of them.
The node N2 is connected to the gate electrode of the n-channel MOS transistor Q2. Since the threshold voltage (V.sub.th) of n-channel MOS transistors Q2 and Q4 is 0.7 V, a subthreshold current of about 1 nA will flow through the n-channel MOS transistor Q2. In this case, the p-channel MOS transistor Q1, which forms the inverter together with the n-channel MOS transistor Q2 connected thereto, is in the ON state because the gate voltage (potential of node N2) is 0.6 V. More specifically, a voltage Vcc (3 V) is applied to the source of p-channel MOS transistor, and the gate voltage viewed from the source is -2.5 V (=0.5 V-3 V). Owing to this fact, the p-channel MOS transistor Q1 is in the ON state, as shown in FIG. 87. The drain current of the p-channel MOS transistor Q1 in the ON state is about 0.5 nA according to FIG. 87, and may be about 1 nA at the maximum.
In this manner, a current which is the subthreshold current flowing through the n-channel MOS transistor Q2 is of a value similar to that of the current flowing through the p-channel MOS transistor Q1. This means that the resistance of p-channel MOS transistor Q1 at the node side (N1 in this case) in the "High" level is equal to the resistance of n-channel transistor Q2 in the reading operation. Therefore, the potential of node N1 is reduced due to the resistance division to a half of the power supply voltage Vcc, i.e., 1.5 V, so that the operation of memory cell becomes unstable and data may be inverted in the worst case. In other words, the charge at the "High" level accumulated in the stray capacitance of node N1 leaks toward the ground potential Vss (0 V) due to the n-channel MOS transistor Q2 through which the subthreshold current flows. In the standby state, since the leak current of the n-channel MOS transistor Q2 is very small and is 1 fA or less, reduction of charge caused by the leak current is supplemented by the p-channel MOS transistor Q1 in the ON state. In the reading operation, however, since the current leaking from the n-channel MOS transistor Q2 is larger than the current supplied from the p-channel MOS transistor Q1, data is destroyed.
Situation of destruction of data will be specified below. The node N1 is connected to the gate electrodes of transistors Q3 and Q4. When the potential of node N1 decreases from 3 V to 1.5 V, a voltage of 1.5 V is applied to the gate electrode of the p-channel MOS transistor Q3. In this operation, the gate voltage viewed from the source side of the transistor Q3 is -1.5 V (=1.5 V-3 V). Therefore, the transistor Q3 which was in the OFF state before the reading operation is turned on in the reading operation (see FIG. 87). Simultaneously with this, the gate voltage of n-channel MOS transistor Q4 lowers from 3 V to 1.5 V. Thereby, the current flowing through the transistor Q4 decreases, and the current flows through the transistor Q3, so that the potential of node N2 rises. When the potential of node N2 increases above the threshold voltage of transistor Q2, i.e., 0.7 V, the transistor Q2 is turned on, and the current larger than the sub-threshold current flows. As a result, the potential of node N1 further lowers. When the potential of node N1 lowers to 0.7 V or less, the gate voltage applied to the transistor Q4 becomes smaller than the threshold, so that the transistor Q4 is turned off. Thereby, the potential of node N2 rises to 3 V, and the potential of node N1 lowers to 0 V. In this manner, the data is inverted in the worst case. Thus, information held in the memory cell is destroyed.
Instability of a memory cell due to reduction of a .beta. ratio described above is specified in H. Shinohara et al., Digest of Technical Papers, Symposium on VLSI Technology (1982), pp 106-107.
A problem in the data writing operation will be discussed below. In the writing operation, a positive voltage is applied to the word line 35 to render the access transistors Q5 and Q6 conductive. The potential of one of the bit lines 33 and 34, which is selected for writing the "Low" level, is set at 0 V for writing data. The operation immediately after the data of "Low" level is written into the node N2 will be discussed below. Although the potential of node N1 is at the "High" level, the access transistor Q5 is in the ON-state, so that the level lowers from Vcc (3 V) to Vcc-Vth (=2 V: Vth is a threshold voltage (1 V) of the access transistor Q5), resulting in an unstable operation of the memory cell. Therefore, the potential of node N1 must be charged by the p-channel MOS transistor Q1 from (Vcc-Vth) to Vcc. The capacity of node N1 is about 1 fF, and the ON-current of p-channel MOS transistor Q1 is 1 nA , so that the time t required for the charging is calculated as t=1 fF.times.1 V/1 nA=1 .mu.sec. Thus, a long time period of about 1 .mu.sec is required until the memory cell attains a stable state. For this time period, information cannot be read from the memory cell. The access time for writing and reading data of SRAM generally must be about 50 nsec. Therefore, TFTs (p-channel MOS transistors) of which ON current is about 1 nA cannot be used for providing memory cells of industrially usable SRAMs.
Then, a problem relating to a standby current of SRAM of 16M bit will be discussed below. A memory cell of complete CMOS SRAM of the TFT load type employs the structure of CMOS inverter. Therefore, it does not include a current path for a direct current, and only a leak current of the transistor contributes to the power consumption of SRAM. In the memory cell in FIG. 83, one of the nodes N1 and N2 holds the potential at "High" level, and the other holds the potential at "Low" level. In the node holding the potential at "High" level, the n-channel MOS transistor Q2 or Q4 is in the OFF state. In the node holding the potential of "Low" level, the p-channel MOS transistor Q1 or Q3 is in the OFF state. The leak currents of n-channel MOS transistors Q2 and Q4 are not more than 1 fA, and the leak currents of p-channel MOS transistors (TFT) Q1 and Q3 are 100 fA (FIG. 87). Therefore, the standby current of the memory cell per one cell is nearly equal to the leak current of one p-channel MOS transistor (TFT). Therefore, the standby current of SRAM of 16M bit is 1.7 .mu.A (=10 fA.times.2.sup.24 cells) exceeding 1 .mu.A, and the SRAM cannot said to achieve low power consumption. In order to achieve the low power consumption, the standby current must be 1 .mu.A or less (preferably, 0.1 .mu.A or less). For this purpose, the leak current of TFT forming the memory cell of SRAM must be 60 fA or less (preferably, 6 fA or less).
From the above description, it is apparent that if the ON current of TFT is small, the memory cell operates unstably during reading and writing of data. In order to avoid this problem, it has been attempted to increase the .beta. ratio of the driver transistor and access transistor. For this purpose, it is necessary to reduce the gate widths W of access transistors Q5 and Q6 and to increase the gate widths W of driver transistors Q2 and Q4. The minimum value of gate width W, however, is determined by the minimum workable size, so that it is impossible to reduce the gate widths of access transistors Q5 and Q6 below this size. Therefore, it is necessary to increase the gate widths W of driver transistors Q2 and Q4 in order to increase the .beta. ratio. However, this increases the chip area of SRAM, and thus makes the miniaturization impossible. In order to increase the .beta. ratio, the threshold voltage Vth of access transistors Q5 and Q6 may be set larger than that of driver transistors Q2 and Q4. Miniaturization of elements, however, requires reduction of the power supply voltage Vcc, so that it becomes more difficult to increase the threshold voltage Vth of access transistors Q5 and Q6 as the degree of integration of SRAM increases.
If the OFF current of TFT is large, the power consumption of SRAM increases. Since the power consumption of SRAM is proportional to the number of TFTs (strictly, it is calculated by (number of TFTs).times.(gate width), and if the degree of integration increases four times, the power consumption increases about three times), the increase of degree of integration of SRAM naturally and unpreferably causes increase of the power consumption if the performance of TFTs is unchanged.
From the above description, it can be understood that the problem that the miniaturized SRAM does not operate correctly is due to the performance of TFTs. Compared with a transistor formed on a substrate of monocrystal silicon, the ON current of TFT is small and the OFF current thereof is large due to crystal grain boundaries of polysilicon existing in a channel portion of TFT.
FIGS. 88A and 88B are a plan and a perspective view of a TFT, respectively, which show the channel region of TFT used in the miniaturized SRAM and a portion there around. The active layer 55 is formed on the gate electrode 60 with the gate insulating film therebetween. The active layer 55 is formed of drain, channel and source regions. The channel region overlaps the gate electrode 60. As shown in the perspective view of FIG. 88B, an average diameter of crystal grains included in a polysilicon film of 300 .ANG. in thickness is determined to be 200 .ANG. by a transmission type electron microscope (TEM). The gate width is 0.4 .mu.m and the gate length is 0.8 .mu.m. Therefore, about 800 crystal grains exist in the channel region of 0.4 .mu.m by 0.8 .mu.m, and about 40 crystal grains exist in a direction parallel to the channel length. As is well known, the grain boundary operates as a trap of carriers (positive holes) in the channel region. The carriers fixed by the trap excludes the carriers near the grain boundaries, and form a potential barrier. Due to the existence of the potential barrier, the electric characteristic of TFT shows phenomena such as lowering of the drain current and lowering of the degree of displacement, as compared with transistors formed on a monocrystal silicon substrate. Therefore, the ON current of TFT decreases. A large number of dangling bonds of silicon atoms exist in the grain boundary. The dangling bonds form a large number of mid-gap levels in the energy band structure of silicon. Electrons are excited from a valence band to a conduction band by thermal excitation through these mid-gap levels, and thus flow from the drain to the source, so that the OFF current of TFT increases. Therefore, it is necessary to increase the grain diameter of polysilicon crystal and to reduce the number of crystal boundaries in order to increase the ON current of TFT and to reduce the OFF current thereof.
In order to increase the grain diameter of polysilicon crystal, there has been known a method in which amorphous silicon is deposited and the solid-phase growth thereof is carried out by annealing the same at a temperature of about 600.degree. C. for several hours for obtaining a polysilicon film of a large grain diameter. There are various method for forming the amorphous silicon. For example, the amorphous silicon is formed by the CVD method at a low temperature of not more than 450.degree. C. using disilane (Si.sub.2 H.sub.6) gas as material. In this method, although the grain diameter of polysilicon can be increased to 1 .mu.m or more, the position at which the grain boundary generates cannot be controlled.
For example, Japanese Patent Laying-Open No. 62-287614 (1987) discloses a method in which an amorphous silicon film is formed at a thickness of 1000 .ANG. or more for increasing the crystal drain diameter of the solid-phase-grown polysilicon film. Further, Japanese Patent Laying-Open No. 2-84773 (1990) discloses a thin-film transistor of which channel region is formed of a crystal region except for a portion including a grain boundary. This reference, however, discloses only a method in which the polysilicon film including grains of a large diameter is obtained from the amorphous silicon film, and does not disclose in any way a method for controlling the position itself in which the grain boundary generates.
For the reasons described above, it is unavoidable that the miniaturized TFT contains grain boundaries existing at a certain rate in the channel region. Further, according to the conventional solid-phase growth method, it is impossible to obtain the TFT provided with a channel region formed of a crystal structure which is controlled to show a large ON current and a small OFF current.